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aktualisiert am 20. Mai 2019

ISBN 9783843912969

Euro 84,00 inkl. 7% MwSt

978-3-8439-1296-9, Reihe Elektrotechnik

Dominik Schrade-Köhn
Gate Module Optimization for GaN HFETs

132 Seiten, Dissertation Universität Ulm (2013), Hardcover, A5

Zusammenfassung / Abstract

One main focus of this work was put on the development of novel processes for the high volume fabrication of GaN HFET devices. Another one was put on process impacts on the GaN surface and the behavior of metal films on the GaN as well as SiN on GaN surfaces. For both, the gate module was the main area of interest, targeting fast processing and good repeatability as well as reliability improvements.


As a replacement for cost-intensive e-beam processing, high throughput lithography processes using robust i-line stepper technology were developed for the gate foot definition. Using commercially available Novolak and BARC resists, a variety of different processes was derived. By introduction of a thermal reflow treatment profile control of the resists’ sidewall was made possible. Part of the processes were proven to be mature enough for industrial purposes whereas one represents a novel way of creating gate lengths below 100 nm.


The gate metal of GaN HFETs is a critical point regarding long term reliability of the devices. Diffusion nvestigations revealed weaknesses of Ni/Au and Ni/Pt/Au contact schemes. The process sequence of an intended Ni-Pt inter-metallic formation followed by a Au deposition was investigated. Novel Ni/WTi/Au and Ni/WSi/Au gate contact schemes are introduced which exhibit clearly separated gate-metal layers even after more than 1200 hours storage at 320 °C.


The process interaction of different process modules with the GaN surface was investigated using available fabrication processes. Additionally several process alternatives were investigated regarding their interaction with the semiconductor surface. The impact of F-ions on pinch-off voltage, leakage currents and Schottky barrier height was characterized on transistor level.


Several novel processes and results from this work were combined in a new process sequence. The presented sequence offers the possibility to avoid process fluctuation in the transistor geometry and to protect the GaN surface from the very beginning of the fabrication sequence.