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978-3-8439-1581-6, Reihe Informatik
Techniques for adapting Industrial Simulation Software for Power Devices and Networks to Multi- and Many-Core Architectures
123 Seiten, Dissertation Technische Universität München (2014), Softcover, A5
Simulation software has been widely used in academic and industrial environments for a long time. In recent years, however, the available hardware characteristics have changed significantly and rapidly. Several years ago, true parallel processing was only available using clusters or expensive workstations, whereas today systems with multiple processor cores are well established and even mass market laptops provide multiple cores.
Contrary to performance increase due to rising processor clock frequency in the past, existing software typically does not automatically benefit from these additional cores and several other improvements. Instead, it has to be adapted to properly benefit from the increased compute power and to efficiently use today’s multi- and many-core architectures.
This thesis devises techniques to cost-effectively conduct these adaptations to increase the efficiency of industrial high voltage engineering applications on multi- and many-core architectures and help to leverage their full potential. This is done using several real world exemplary simulation software packages provided by industry partner ABB.
The presented techniques include strategic changes to data structures and algorithms to improve time complexity by subtly inserting caches or extending data access methods where appropriate. Other changes improve performance by accounting for characteristic properties of processor hardware, such as caches or branch prediction - ultimately by dynamically generating optimized and highly problem specific code.
Additionally, the implications of reimplementing an application based on new and improved theoretical methods regarding performance as well as cost-effective development are discussed and evaluated.
Finally, various application characteristics and runtime parameters affecting parallel efficiency are illustrated on both general purpose multi-core processors as well as a Xeon Phi system representing a many-core architecture.