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aktualisiert am 10. Juli 2019

ISBN 9783843917698

Euro 72,00 inkl. 7% MwSt

978-3-8439-1769-8, Reihe Elektrotechnik

Björn Osterloh
Reliable dynamic partial hardware reconfiguration in space applications

161 Seiten, Dissertation Technische Universität Braunschweig (2014), Softcover, A5

Zusammenfassung / Abstract

Data Processing Units (DPUs) are commonly used for operational control and application-specific data processing of scientific space instruments. However, for operation in the harsh space environment DPUs need to be robust and fault-tolerant. The evolution of space missions indicates a trend towards high-resolution sensors and, as a result, extremely high data volumes. Consequently, DPUs for future space missions demand high-performance on-board processing due to the discrepancy between the high data volume and low downlink channel capacity. Furthermore, classical ground processing steps such as subsequent data evaluation must be performed on-board. These processing steps often require adaptation during the space mission and there is thus a need for adaptable on-board processing. Today, radiation-tolerant space-grade SRAM-based FPGAs provide a highly flexible platform. These devices can be partially or completely reconfigured, even during operation. Currently, their reconfigurability is only used during the development phase. A logical next step would be to exploit the reconfigurability of SRAM-FPGAs in space, either to statically update or to dynamically reconfigure processing modules. This is potentially a major improvement in terms of maintenance and performance. The requirement for such an enhanced system is to guarantee the system qualification while retaining high reliability. Therefore, effects e.g. during the reconfiguration process and interference of updated modules on the system must be prevented. Updated modules need to be physically and logically isolated from the system by a qualified communication architecture. Classical bus-based communication architectures are limited in this sense and do not provide isolation of reconfigurable modules. Therefore, an advanced, robust and fault-tolerant on-chip communication architecture is required. The Network-on-Chip (NoC) paradigm provides advantageous features with e.g. fault-tolerant error detection/recovery schemes. Thus, a NoC approach-utilising System-on-Chip Wire (SoCWire) based on the ESA SpaceWire standard has been developed which provides isolation of reconfigurable modules with guaranteed system qualification. High data rates are achieved with modest implementation effort. Hardware error detection and hot-plug ability are supported. SoCWire provides a robust and fault-tolerant on-chip communication architecture for future space applications with adaptable high-performance on-board processing.