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aktualisiert am 19. Mai 2024

ISBN 9783843937290

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978-3-8439-3729-0, Reihe Elektrotechnik

Feng Yu
Vertical Field-Effect Transistors Based on 3D GaN Nanowire Arrays

174 Seiten, Dissertation Technische Universität Braunschweig (2018), Softcover, A5

Zusammenfassung / Abstract

A novel concept of realizing three-dimensional (3D) GaN nanowire-based FETs has been proposed and proved, through delicate device design and processing. In particular, 3D FETs are directly processed on massive vertical GaN nanowires as prepared, rather than harvesting and transferring them onto some foreign substrates. In addition, normal UV lithography, instead of e-beam type, is employed for nano-device fabrication, which is essential for industrial mass production. Compared to their conventional lateral counterparts, 3D GaN nanowire-based FETs have the unique advantages in realizing wrap-around gate structure and vertical electrode layout, which can potentially provide superior electrostatic gate control and high driving current capability. In this thesis, a top-down hybrid etching technique is introduced for preparing c-axis GaN vertical nanowire arrays, and the etching dynamic is systematically discussed as well. The polarization-field-free sidewalls and small substrate footprints of c-axis GaN nanowires are prospective for realizing enhancement mode operation and avoiding strain issues.

Besides, the theoretical insights of the device performances are systematically investigated by simulation tool Synopsys Sentaurus TCAD. The results indicate that both enhancement and depletion mode GaN nanowire FETs are feasible through proper control in channel doping and wire dimension, which reveals one strategy advantage of the top-down approach since etching on mature grown epitaxial films results in a selective-area doping in wire axial direction. In particular, the on-resistance as well as the electric field distribution in 3D GaN nano-FETs is studied to explore the potential applications in power switching.

In the end, the fabricated 3D GaN nanowire array-based FETs have been electrically characterized, in terms of DC, capacitance-voltage, and transient properties. The devices exhibit some promising performances, including enhancement mode operation, high on an off current ratio, small subthreshold swing, and small leakage. Despite the challenges in stray impedance and gate memory effect, the 3D architecture provides a new rout towards next generation GaN-based transistors.